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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd720130 usb2.0 to ide bridge document no. s16302ej3v0ds00 (3rd edition) date published june 2003 ns cp (k) printed in japan data sheet the mark shows major revised points. 2002 the pd720130 is designed to perform a bridge between usb 2.0 and ata/atapi. the pd720130 complies with the universal serial bus specification revision 2.0 full-/high-speed signaling and works up to 480 mbps. the pd720130 is integrated cisc processor, ata/atapi controller, endpoint controller (epc), serial interface engine (sie), and usb2.0 transceiver into a single chip. the usb2.0 protocol and class specific protocol (bulk only protocol) are handled by usb2.0 transceiver, sie, and epc. and the transport layer is performed by v30mz cisc processor which is in the pd720130. the software to control the pd720130 is located in an embedded rom. in the future, the pd720130 will be released to support external flash memory / eeprom? option to update function by firmware. detailed function descriptions are provided in the following user?s manual. be sure to read the manual before designing. pd720130 user?s manual: s16412e features compliant with universal serial bus specification revision 2.0 (data rate 12/480 mbps) compliant with ata/atapi-6 (lba48, pio mode 0-4, multi word dma mode 0-2, ultra dma mode 0-4) usb2.0 high-speed bus powered device capability certified by usb implementers forum and granted with usb 2.0 high-speed logo (tid :40320125) one usb2.0 high-speed transceiver / receiver with full-speed transceiver / receiver usb2.0 high-speed or full-speed packet protocol sequencer (serial interface engine) automatic chirp assertion and full-/high-speed mode change usb reset, suspend and resume signaling detection supports power control functionality for ide device as cd-rom and hdd supports set feature (test_mode) functionality system clock is generated by 30 mhz x?tal 2.5 v and 3.3 v power supply ordering information part number package pd720130gc-9eu 100-pin plastic tqfp (fine pitch) (14 14) pd720130gc-9eu-sin 100-pin plastic tqfp (fine pitch) (14 14)
data sheet s16302ej3v0ds 2 pd720130 block diagram ram 4 kbytes 2 cpu core (v30mz) bus bridge rom 8 kbytes dmac intc direct bus 16-bit bus pio fsio timer idec_v2 epc2_v2 dcc phy_v2 gpio direct command bus ext. bus (data 8-bit bus) or pio ide bus serial rom 8-bit bus gpio or fsio usb bus 16-bit bus v30mz : cisc cpu core ram : 8-kbyte work ram for firmware rom : 8-kbyte rom for built-in firmware phy_v2 : usb2.0 transceiver with serial interface engine epc_v2 : endpoint controller idec_v2 : ide controller dcc : ata direct command controller bus bridge : internal / external bus controller and dma controller intc : interrupt controller (82c59 like) gpio : general purpose 8-bit i/o controller pio : multipurpose 14-bit i/o controller fsio : flexible serial i/o
data sheet s16302ej3v0ds 3 pd720130 pin configuration (top view) ? 100-pin plastic tqfp (fine pitch) (14 14) pd720130gc-9eu pd720130gc-9eu-sin v dd25 v dd33 gpio1 dv0 gpio2 pio15 gpio0 gpio3 idea2 gpio7 idea0 idea1 v ss ideiordy idedakb ideint ideiorb test0 test1 test3 v dd33 v dd25 scl v ss dpc sda test2 v dd25 rpu v dd25 v ss rsdp dp v dd33 dm rsdm v ss av dd25 av ss rref v ss smc ided5 v ss v dd33 iderstb ided7 ided8 ided6 ided10 ided9 ided4 ided11 ided3 ided12 v ss v dd25 ided2 ided13 ided14 ided1 v dd33 ided0 ided15 gpio4 idedrq ideiowb v ss v dd25 clc cmb_state pwr v dd25 v dd33 pio5 v dd33 cmb_bsy vbus v dd25 av ss av dd25 av ss (r) v ss idecs0b gpio5 md1 irq0 resetb spd v ss v dd33 gpio6 md0 v ss idecs1b xout xin dcc pio14 dv1 1 5 10 15 20 25 30 40 45 35 50 55 60 65 70 75 85 90 100 80 95
data sheet s16302ej3v0ds 4 pd720130 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v dd25 26 v ss 51 v dd25 76 v ss 2v dd33 27 ideiowb 52 v dd33 77 dpc 3 xin 28 idedrq 53 gpio7 78 sda 4 xout 29 ided15 54 gpio6 79 scl 5v ss 30 ided0 55 gpio5 80 test2 6 resetb 31 v dd33 56 gpio4 81 v dd25 7v dd33 32 ided14 57 gpio3 82 rpu 8 irq0 33 ided1 58 gpio2 83 v dd25 9 md0 34 ided13 59 gpio1 84 v ss 10 md1 35 ided2 60 v ss 85 rsdp 11 idecs1b 36 v dd25 61 gpio0 86 dp 12 idecs0b 37 v ss 62 pio15 87 v dd33 13 idea2 38 ided12 63 pio14 88 dm 14 idea0 39 ided3 64 dcc 89 rsdm 15 idea1 40 ided11 65 dv1 90 v ss 16 v ss 41 ided4 66 dv0 91 av dd25 17 ideint 42 ided10 67 v ss 92 av ss 18 idedakb 43 v dd33 68 spd 93 rref 19 ideiordy 44 ided5 69 clc 94 av ss (r) 20 ideiorb 45 ided9 70 pwr 95 av dd25 21 test0 46 ided6 71 cmb_bsy 96 av ss 22 test1 47 ided8 72 pio5 97 v dd25 23 test3 48 ided7 73 cmb_state 98 vbus 24 v dd33 49 iderstb 74 v dd33 99 smc 25 v dd25 50 v ss 75 v dd25 100 v ss remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 2.43 k ? .
data sheet s16302ej3v0ds 5 pd720130 1. pin information (1/2) pin name i/o buffer type active level function xin i 2.5 v input system clock input or oscillator in xout o 2.5 v output oscillator out resetb i 3.3 v schmitt input low asynchronous reset signaling md(1:0) i 3.3 v input function mode setting idecs(1:0)b o (i/o) 5 v tolerant output low ide host chip select idea(2:0) o (i/o) 5 v tolerant output ide address bus ideint i (i/o) 5 v tolerant input high ide interrupt request from device to host idedakb o (i/o) 5 v tolerant output low ide dma acknowledge ideiordy i (i/o) 5 v tolerant input high ide io channel ready ideiorb o (i/o) 5 v tolerant output low ide io read strobe ideiowb o (i/o) 5 v tolerant output low ide io write strobe idedrq i (i/o) 5 v tolerant input high ide dma request from device to host ided(15:0) i/o 5 v tolerant i/o ide data bus iderstb o (i/o) 5 v tolerant output low ide reset from host to device dcc i (i/o) 3.3 v input ide controller operational mode setting dv(1:0) i (i/o) 3.3 v input device select clc i (i/o) 3.3 v input system clock setting pwr i (i/o) 3.3 v input bus powered /self-powered select cmb_bsy o (i/o) 3.3 v output combo ide bus busy cmb_state i (i/o) 3.3 v input combo ide bus state dpc o (i/o) 3.3 v output power control signaling for ide device sda i/o 3.3 v i/o serial rom data signaling scl i/o 3.3 v i/o serial rom clock signaling vbus i 5 v schmitt input note vbus monitoring dp i/o usb high speed d+ i/o usb ? s high speed d+ signal dm i/o usb high speed d ? i/o usb ? s high speed d ? signal rsdp o usb full speed d+ output usb ? s full speed d+ signal rsdm o usb full speed d ? output usb ? s full speed d ? signal rpu a usb pull-up control usb ? s 1.5 k ? pull-up resistor control rref a analog reference resistor spd i (i/o) 3.3 v input nec private smc i 3.3 v input scan mode control test(3:0) i 3.3 v input test mode setting note vbus pin may be used to monitor for vbus line even if v dd33 , v dd25 , and av dd25 are shut off. system must ensure that the input voltage level for vbus pin is less than 3.0 v due to the absolute maximum rating is not exceeded.
data sheet s16302ej3v0ds 6 pd720130 (2/2) pin name i/o buffer type active level function gpio(7:0) i/o 3.3 v schmitt i/o general purpose io port (for future extension) pio(15:14) i/o 3.3 v i/o io port (for future extension) pio(5) i/o 3.3 v schmitt i/o io port (for future extension) irq0 i 3.3 v schmitt input high external interrupt input (for future extension) av dd25 2.5 v v dd for analog circuit v dd25 2.5 v v dd v dd33 3.3 v v dd av ss v ss for analog circuit v ss v ss remarks 1. ? 5 v tolerant ? means that the buffer is 3.3 v buffer with 5 v tolerant circuit. 2. the signal marked as ? (i/o) ? in the above table operates as i/o signals during testing. however, they do not need to be considered in normal use.
data sheet s16302ej3v0ds 7 pd720130 2. function information usb to ide system can be realized by the pd720130, serial rom which has usb vender id, product id, etc, and power control circuit. the pd720130 can be selected bus powered mode or self powered mode. if all power consumption for usb to ide system is less than the specification of bus powered device, it will be possible to realize high-speed capable bus powered system. the pd720130 has some features for bus powered system. also, some system may control target ide device by two ide controllers. at the time, ide bus arbitration should be required to each ide controller. the pd720130 has a feature of ide bus arbitration, too. the setting of ide controller in the pd720130 is controlled by data in serial rom or external pin setting. if there is any inconsistency between data in serial rom and external pin setting, the data in serial rom is higher priority than external pin setting. 2.1 data in serial rom the pd720130 loads some data such as vendor id, product id and some additional usb related information, etc from serial rom when the pd720130 is initialized. example of data in serial rom is as follows. expinreset and expinset fields hold data which is related to the external pin setting. table 2-1. data in serial rom data size symbol description 1 word flags control for descriptor overwrite 1 byte expinreset pwr, clc, dcc, dv[1:0] reset bit map field 1 byte expinset pwr, clc, dcc, dv[1:0] set bit map field 1 word idvendor idvendor field in device descriptor 1 word idproduct idproduct field in device descriptor 1 word bcddevice bcddevice field in device descriptor 1 byte maxpower bus maxpower field in configuration descriptor for bus powered mode 1 byte maxpower self maxpower field in configuration descriptor for self powered mode 1 byte binterfaceclass binterfaceclass field in interface descriptor 1 byte binterfacesubclass binterfacesubclass field in interface descriptor 1 byte binterfaceprotocol binterfaceprotocol field in interface descriptor 1 word txmode reset ide transmission type such as ultra dma 66 reset bit map field 1 word txmode set ide transmission type such as ultra dma 66 set bit map field 32 bytes manufacturestring string descriptor for manufacturer 32 bytes productstring string descriptor for product 32 bytes serialstring string descriptor for device serial number
data sheet s16302ej3v0ds 8 pd720130 2.2 external pin setting usually, serial rom should be used to keep vendor id, product id and some additional usb related information. and then, the external pin setting of the pd720130 is not so important to realize usb to ide bridge system. the recommended external pin setting is as follows. table 2-2. recommended external pin setting pin name setting md1 1 md0 0 scl pull up note 1 sda pull up dv1 ? l ? clamp dv0 ? l ? clamp clc ? l ? clamp pwr ? l ? clamp dcc pull down note 2 gpio(7:0) ? l ? clamp pio(14:15) ? l ? clamp pio5 ? l ? clamp spd ? h ? clamp test(3:0) ? l ? clamp smc ? l ? clamp irq0 ? l ? clamp notes 1. if serial rom size is more than 2 kbytes, scl should be pull down. 2. if target ide device is not fixed, it is preferable that dcc pin can switch pull-up or pull-down. the setting for any other pins such as cmb_bsy, cmb_state depends on usb2.0 to ide bridge system. for example, if two ide controllers control one target ide device and one of two ide controllers is the pd720130, cmb_bsy and cmb_state are used to handshake between two ide controller chips. on the other hand, when the pd720130 is only controller of target ide device, cmb_bsy should be opened and cmb_state should be clamped to ? l ? .
data sheet s16302ej3v0ds 9 pd720130 2.3 control bit in serial rom or external pin setting the following tables show ide status and control bit in serial rom or external pin setting. table 2-3. dv1/dv0, clc, pwr setting setting in serial rom or external pin no. device power internal clock ata/atapi pwr clc dv1 dv0 0 no device connected 1 1 1 1 1ata1110 2atapi1101 3 7.5 mhz reserved 1 1 0 0 4 no device connected 1 0 1 1 5ata1010 6atapi1001 7 bus powered 60 mhz reserved 1 0 0 0 8 no device connected 0 1 1 1 9 combo (ata) 0 1 1 0 10 combo (atapi) 0 1 0 1 11 reserved 0 1 0 0 12 no device connected 0 0 1 1 13 ata 0 0 1 0 14 atapi 0 0 0 1 15 self powered 60 mhz auto device detect 0 0 0 0 remark setting no. 0, 3, 4, 7, 8, 11, and 12 are prohibited to use.
data sheet s16302ej3v0ds 10 pd720130 table 2-4. dv1/dv0, dcc setting condition dv1 dv0 mode target device dcc pin setting dcc setting in serial rom description 0 no setting ultra, multi word dma are disabled 0 reset ultra, multi word dma are disabled 0 set ultra, multi word dma are enabled. 1 no setting ultra, multi word dma are enabled. 1 reset ultra, multi word dma are disabled 10ataata 1 set ultra, multi word dma are enabled. 0 no setting ultra dma is disabled 0 reset ultra dma is disabled 0 set ultra, multi word dma are enabled. 1 no setting ultra, multi word dma are enabled. 1 reset ultra dma is disabled 0 1 atapi atapi 1 set ultra, multi word dma are enabled. 0 no setting ultra, multi word dma are disabled 0 reset ultra, multi word dma are disabled 0 set ultra, multi word dma are enabled. 1 no setting ultra, multi word dma are enabled. 1 reset ultra, multi word dma are disabled ata 1 set ultra, multi word dma are enabled. 0 no setting ultra dma is disabled 0 reset ultra dma is disabled 0 set ultra, multi word dma are enabled. 1 no setting ultra, multi word dma are enabled. 1 reset ultra dma is disabled 00 auto device detect atapi 1 set ultra, multi word dma are enabled. remark pio mode 0-4 are always enabled.
data sheet s16302ej3v0ds 11 pd720130 2.4 combo mode function the pd720130 can be used to realize that two ide controller chips control one target ide device in one system. to realize ide bus arbitration between two ide controller chips, the pd720130 has cmb_bsy and cmb_state. combo mode is enabled when pwr = 0 and clc = 1. cmb_bsy and cmb_state connect to other ide controller chip as follows. figure 2-1. cmb_bsy and cmb_state connection between two ide controller chips other ide controller ide bus request pd720130 cmb_state cmb_bsy ide bus grant table 2-5. description of cmb_bsy and cmb_state pin name direction value description 0 other ide controller does not require or does not use ide bus. cmb_state in 1 other ide controller requires or is using ide bus. 0 the pd720130 does not require or does not use ide bus. cmb_bsy out 1 the pd720130 requires or is using ide bus.
data sheet s16302ej3v0ds 12 pd720130 the ide bus arbitration will be done by following sequence. the pd720130 will confirm whether other ide controller requires or is using ide bus or not. if other ide controller does not require or does not use ide bus, the pd720130 will use ide bus. figure 2-2. ide bus arbitration sequence start chip init cmb_bsy = 1 cmb_state = 1? cmb_state = 0? cmb_bsy = 0 yes. no. other ide controller requires or is using ide bus. no. ide bus is used yes. end the pd720130 can not use ide bus by the pd720130
data sheet s16302ej3v0ds 13 pd720130 2.5 power control to realize bus-powered or high performance self-powered usb2.0 to ide bridge system, the pd720130 has two internal system clock mode. one is 7.5 mhz for bus-powered mode and the other is 60 mhz for self-powered mode. the pd720130 controls the power state by events as follows. the word with under line shows event. the italic word shows the power state. figure 2-3. power state control (a) bus-powered mode idle mode vbus off vbus on connect set configuration resume resume suspend hardware reset bus reset power off set configuration resume resume suspend suspend fs connect hs connect power = p enum_fs power = p enum_hs suspend suspend resume suspend resume power = p fs_b power = p hs_b power = p spnd power = p spnd power = p reset hs enumeration state suspend mode hs operation state fs operation state configured state fs enumeration state suspend mode configured state power off default state (b) self-powered mode power = p spnd power on vbus off vbus on connect set configuration resume resume suspend hardware reset bus reset power off set configuration resume resume suspend suspend fs connect hs connect power = p enum_fs power = p enum_hs power = p combo suspend suspend resume suspend resume power = p fs_s power = p hs_s power = p spnd power = p reset cmb_state = 0 cmb_state = 1 power off ide bus release state idle mode default state suspend mode hs operation state disconnect mode fs operation state configured state fs enumeration state suspend mode hs enumeration state configured state
data sheet s16302ej3v0ds 14 pd720130 to realize bus-powered usb2.0 to ide bridge system, the power consumption for ide device should be controlled by the power state of the pd720130. the pd720130 has dpc pin to control ide device ? s power circuit. dpc pin ? s output level relates to usb device states. dpc should be pull up to 3.3 v because dpc output becomes high impedance state until the pd720130 is initialized. figure 2-4. dpc pin to control ide device ? s power circuit dpc power on hardware reset bus reset set configuration un-configured default configured suspend occured resume occured suspend configured normal operation normal operation high impedance state following reference circuit can cut off power supply to ide device during the pd720130 is under default and un-configured state. also, the power supply to ide device is disabled during suspend state, too. power consumption of total system under default, un-configured, and suspend state can be reduced by dpc pin. figure 2-5. power control circuit example p-channel switch on pull up 3.3 v in out regulator power supply rail ide device power dpc pd720130
data sheet s16302ej3v0ds 15 pd720130 3. electrical specifications 3.1 buffer list ? 2.5 v oscillator interface xin, xout ? 3.3 v input buffer md(1:0), test(3:0), smc ? 3.3 v schmitt input buffer resetb, irq0 ? 3.3 v input buffer with enable (or type) dcc, dv(1:0), spd, clc, pwr, cmb_state ? 3.3 v i ol = 6 ma 3-state output buffer cmb_bsy, dpc ? 3.3 v i ol = 3 ma bi-directional schmitt buffer with input enable (or-type) gpio(7:0), pio5, sda, scl ? 3.3 v i ol = 6 ma bi-directional buffer with input enable (or-type) pio(15:14) ? 5 v schmitt input buffer vbus ? 5 v i ol = 6 ma 3-state output buffer idecs(1:0)b, idea(2:0), idedakb, ideiorb, ideiowb, iderstb ? 5 v i ol = 6 ma bi-directional buffer with input enable (or-type) ided(15:0), ideint, ideiordy, idedrq ? usb interface dp, dm, rsdp, rsdm, rref, rpu remark above, ? 5 v ? refers to a 3.3 v buffer with 5-v tolerant circuit. therefore, it is possible to have a 5-v connection for an external bus, but the output level will be only up to 3.3 v, which is the v dd33 voltage.
data sheet s16302ej3v0ds 16 pd720130 3.2 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd33 , v dd25 indicates voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates absolute tolerance value for dc current to prevent damage or reduced reliability when a current flows out of or into an output pin. operating temperature t a indicates the ambient temperature range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. terms used in recommended operating range parameter symbol meaning power supply voltage v dd33 , v dd25 indicates the voltage range for normal logic operations occur when v ss = 0 v. high-level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ? min. ? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ? max. ? value is applied, the input voltage is guaranteed as low level voltage. hysteresys voltage v h indicates the differential between the positive trigger voltage and the negative trigger voltage. input rise time t ri indicates allowable input rise time to input pins. input rise time is transition time from 0.1 v dd to 0.9 v dd . input fall time t fi indicates allowable input fall time to input pins. input fall time is transition time from 0.9 v dd to 0.1 v dd . terms used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. output short circuit current i os indicates the current that flows when the output pin is shorted (to gnd pins) when output is at high-level. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that flows from the output pins when the rated high-level output voltage is being applied.
data sheet s16302ej3v0ds 17 pd720130 3.3 electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd33 v dd25 3.3 v power supply rail 2.5 v power supply rail ? 0.5 to + 4.6 ? 0.5 to + 3.6 v v input voltage, 5 v buffer v i 3.0 v v dd33 3.6 v v i < v dd33 + 3.0 v ? 0.5 to + 6.6 v input voltage, 3.3 v buffer v i 3.0 v v dd33 3.6 v v i < v dd33 + 1.0 v ? 0.5 to + 4.6 v input voltage, 2.5 v buffer v i 2.3 v v dd25 2.7 v v i < v dd25 + 0.9 v ? 0.5 to + 3.6 v output voltage, 5 v buffer v o 3.0 v v dd33 3.6 v v o < v dd33 + 3.0 v ? 0.5 to + 6.6 v output voltage, 3.3 v buffer v o 3.0 v v dd33 3.6 v v o < v dd33 + 1.0 v ? 0.5 to + 4.6 v output voltage, 2.5 v buffer v o 2.3 v v dd25 2.7 v v o < v dd25 + 0.9 v ? 0.5 to + 3.6 v output current, 5 v buffer i o i ol = 6 ma 20 ma output current, 3.3 v buffer i o i ol = 6 ma i ol = 3 ma 20 10 ma ma operating ambient temperature t a 0 to + 70 c storage temperature t stg ? 65 to + 150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. two power supply rails limitation the pd720130 has two power supply rails (2.5 v, 3.3 v). the system will require the time when power supply rail is stable at v dd level. and, there will be difference between the time of v dd25 and v dd33 . the pd720130 requires that v dd25 should be stable before v dd33 becomes stable. at this case, the system must ensure that the absolute maximum ratings for v i / v o are not exceeded. system reset signaling should be asserted more than specified time after both v dd25 and v dd33 are stable.
data sheet s16302ej3v0ds 18 pd720130 recommended operating ranges parameter symbol condition min. typ. max. unit operating voltage v dd33 3.3 v for v dd33 pins 3.0 3.3 3.6 v v dd25 2.5 v for v dd25 pins 2.3 2.5 2.7 v v dd25 2.5 v for av dd25 pins 2.3 2.5 2.7 v high-level input voltage v ih 5.0 v high-level input voltage 2.0 5.5 v 3.3 v high-level input voltage 2.0 v dd33 v 2.5 v high-level input voltage 1.7 v dd25 v low-level input voltage v il 5.0 v low-level input voltage 0 0.8 v 3.3 v low-level input voltage 0 0.8 v 2.5 v low-level input voltage 0 0.7 v hysteresis voltage v h 5 v hysteresis voltage 0.3 1.5 v 3.3 v hysteresis voltage 0.2 1.0 v input rise time t ri normal buffer 0 200 ns schmitt buffer 010ms input fall time t fi normal buffer 0 200 ns schmitt buffer 010ms
data sheet s16302ej3v0ds 19 pd720130 dc characteristics (v dd33 = 3.0 to 3.6 v, v dd25 = 2.3 to 2.7 v, t a = 0 to + + + + 70 c) control pin block parameter symbol condition min. max. unit off-state output current i oz v o = v dd33, v dd25 or v ss 10 a output short circuit current i os note ? 250 ma low-level output current 5.0 v low-level output current 3.3 v low-level output current 3.3 v low-level output current i ol v ol = 0.4 v v ol = 0.4 v v ol = 0.4 v 6.0 6.0 3.0 ma ma ma high-level output current 5.0 v high-level output current 3.3 v high-level output current 3.3 v high-level output current i oh v oh = 2.4 v v oh = 2.4 v v oh = 2.4 v ? 2.0 ? 6.0 ? 3.0 ma ma ma input leakage current 3.3 v buffer 5.0 v buffer i i v i = v dd or v ss v i = v dd or v ss 10 10 a a note the output short circuit time is one second or less and is only for one pin on the lsi.
data sheet s16302ej3v0ds 20 pd720130 usb interface block parameter symbol conditions min. max. unit serial resistor between dp (dm) and rsdp (rsdm) r s 38.61 39.39 ? output pin impedance z hsdrv includes r s resistor 40.5 49.5 ? bus pull-up resistor on upstream facing port r pu 1.5 k ? 5% consists of resistance of transistor and pull-up resistor 1.485 1.515 ? termination voltage for upstream facing port pull-up v term 3.0 3.6 v input levels for full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 low-level input voltage v il 0.8 v differential input sensitivity v di ? (d+) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for full-speed: high-level output voltage v oh r l of 14.25 k ? to v ss 2.8 3.6 v low-level output voltage v ol r l of 1.425 k ? to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch detection threshold (differential signal) v hssq 100 150 mv high-speed disconnect detection threshold (differential signal) v hsdsc 525 625 mv high-speed data signaling common mode voltage range v hscm ? 50 + 500 mv high-speed differential input signaling level see figure 3-4 . output levels for high-speed: high-speed idle state v hsoi ? 10.0 + 10.0 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10.0 + 10.0 mv chirp j level (differential signal) v chirpj 700 1100 mv chirp k level (differential signal) v chirpk ? 900 ? 500 mv
data sheet s16302ej3v0ds 21 pd720130 figure 3-1. differential input sensitivity range for low-/full-speed 4.6 ? 1.0 input voltage range (v) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 3-2. full-speed buffer v oh /i oh characteristics for high-speed capable transceiver max. min. ? 80 ? 60 ? 40 ? 20 0 v dd ? 0.3 v out (v) i out (ma) v dd ? 2.3 v dd ? 3.3 v dd ? 0.8 v dd v dd ? 1.3 v dd ? 1.8 v dd ? 2.8 figure 3-3. full-speed buffer v ol /i ol characteristics for high-speed capable transceiver max. min. 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma)
data sheet s16302ej3v0ds 22 pd720130 figure 3-4. receiver sensitivity for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 5 point 2 point 1 point 3 point 4 point 6 figure 3-5. receiver measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ? pin capacitance parameter symbol condition min. max. unit input capacitance c in 46pf output capacitance c out 46pf i/o capacitance c io v dd = 0 v, t a = 25 c f c = 1 mhz unmeasured pins returned to 0 v 46pf
data sheet s16302ej3v0ds 23 pd720130 power consumption (1) the power consumption when device works as bus-powered mode symbol condition max. unit v dd25 v dd33 av dd25 the power consumption under unconfigured stage p enum-bus high-speed operating full-speed operating 57 23 3 4 10 10 ma ma the power consumption when device works p w-bus high-speed operating full-speed operating 110 113 22 13 10 10 ma ma p w_spd-bus the power consumption under suspend state 10 235 5 a (2) the power consumption when device works as self-powered mode symbol condition max. unit v dd25 v dd33 av dd25 the power consumption under unconfigured stage p enum-self high-speed operating full-speed operating 85 60 5 5 10 10 ma ma the power consumption when device works p w-self high-speed operating full-speed operating 120 113 25 13 10 10 ma ma p w_spd-self the power consumption under suspend state 50 5 5 ma p w_unp the power consumption under unplug state 87 3 10 ma p w_com the power consumption under combo mode the device is releasing the ide bus. 90 5 10 ma
data sheet s16302ej3v0ds 24 pd720130 ac characteristics (v dd33 = 3.0 to 3.6 v, v dd25 = 2.3 to 2.7 v, t a = 0 to + + + + 70 c) system clock ratings parameter symbol condition min. typ. max. unit x ? tal ? 500 ppm 30 + 500 ppm mhz clock frequency f clk oscillator block ? 500 ppm 30 + 500 ppm mhz clock duty cycle t duty 45 50 55 % remarks 1. recommended accuracy of clock frequency is 100 ppm. 2. required accuracy of x ? tal or oscillator block is including initial frequency accuracy, the spread of x ? tal capacitor loading, supply voltage, temperature, and aging, etc. system reset signaling parameter symbol conditions min. max. unit reset active time t rst 2 s usb interface block (1/2) parameter symbol conditions min. max. unit full-speed source electrical characteristics rise time (10% - 90%) t fr c l = 50 pf, r s = 36 ? 420ns fall time (90% - 10%) t ff c l = 50 pf, r s = 36 ? 420ns differential rise and fall time matching t frfm (t fr /t ff ) 90 111.11 % full-speed data rate for device which are high-speed capable t fdraths average bit rate 11.9940 12.0060 mbps frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4.0 + 3.5 + 4.0 ns ns source jitter for differential transition to se0 transition t fdeop ? 2 + 5 ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 + 18.5 + 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns
data sheet s16302ej3v0ds 25 pd720130 (2/2) parameter symbol conditions min. max. unit high-speed source electrical characteristics rise time (10% - 90%) t hsr 500 ps fall time (90% - 10%) t hsf 500 ps driver waveform see figure 3-6 . high-speed data rate t hsdrat 479.760 480.240 mbps microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high- speed bit times data source jitter see figure 3-6 . receiver jitter tolerance see figure 3-4 . device event timings time from internal power good to device pulling d+ beyond v ihz (min.) (signaling attached) t sigatt 100 ms debounce interval provided by usb system software after attach t attdb 100 ms inter-packet delay for full-speed t ipd 2bit times inter-packet delay for device response w/detachable cable for full-speed t rspipd1 6.5 bit times high-speed detection start time from suspend t sca 2.5 s sample time for suspend vs reset t csr 100 875 s time to detect bus suspend state t spd 3.000 3.125 ms power down under suspend t sus 10 ms reversion time from suspend to high- speed t rhs 1.333 s drive chirp k width t cko 1ms finish chirp k assertion t fca 7ms start sequencing chirp k-j-k-j-k-j t ssc 100 s finish sequencing chirp k-j t fsc ? 500 ? 100 s detect sequencing chirp k-j width t csi 2.5 s sample time for sequencing chirp t scs 12.5ms reversion time to high-speed t rha 500 s high-speed detection start time t hds 2.5 3000 s reset completed time t drs 10 ms
data sheet s16302ej3v0ds 26 pd720130 ide interface block pio mode parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit cycle time (min.) t 0 600 383 240 180 120 ns address setup time (min.) t 1 70 50 30 30 25 ns 16 bits dior/diow pulse width (min.) t 2 165 125 100 80 70 ns 8 bits dior/diow pulse width (min.) 290 290 290 80 70 ns dior/diow recovery time (min.) t 2i ??? 70 25 ns diow data setup time (min.) t 3 60 45 30 30 20 ns diow data hold time (min.) t 4 30 20 15 10 10 ns dior data setup time (min.) t 5 50 35 20 20 20 ns dior data hold time (min.) t 6 5 5 555 ns dior 3-state delay time (max.) t 6z 30 30 30 30 30 ns address hold time (min.) t 9 20 15 10 10 10 ns iordy read data valid time (min.) note t rd 0 0 000 ns iordy setup time (min.) note t a 35 35 35 35 35 ns iordy pulse width (max.) note t b 1250 1250 1250 1250 1250 ns iordy inactive to hi-z time (max.) note t c 5 5 555 ns note iordy is an option in mode 0 - 2. iordy is essential in modes 3 and 4. multi word dma mode parameter symbol mode 0 mode 1 mode 2 unit cycle time (min.) t 0 480 150 120 ns dior/diow pulse width (min.) t d 215 80 70 ns dior data access time (max.) t e 150 60 50 ns dior data hold time (min.) t f 555ns dior data setup time (min.) t gr 100 30 20 ns diow data setup time (min.) t gw 100 30 20 ns diow data hold time (min.) t h 20 15 10 ns dmack setup time (min.) t i 000ns dmack hold time (min.) t j 20 5 5 ns dior negate pulse width (min.) t kr 50 50 25 ns diow negate pulse width (min.) t kw 215 50 25 ns dior-dmarq delay time (max.) t lr 120 40 35 ns diow-dmarq delay time (max.) t lw 40 40 35 ns dmack 3-state delay time (max.) t z 20 25 25 ns cs setup time (min.) t m 50 30 25 ns cs hold time (min.) t n 15 10 10 ns
data sheet s16302ej3v0ds 27 pd720130 ultra dma mode mode 0 mode 1 mode 2 mode 3 mode 4 parameter symbol min. max. min. max. min. max. min. max. min. max. unit average cycle time for 2 cycles t 2cyc 240 - 160 - 120 - 90 - 60 - ns minimum cycle time for 2 cycles t 2cyc 235 - 156 - 117 - 86 - 57 - ns cycle time for 1 cycle t cyc 114 - 75 - 55 - 39 - 25 - ns data setup time on receive side t ds 15-10-7-7-5- ns data hold time on receive side t dh 5-5-5-5-5- ns data setup time on transmit side t dvs 70 - 48 - 34 - 20 - 6 - ns data hold time on transmit side t dvh 6-6-6-6-6- ns first strobe time t fs 0 230 0 200 0 170 0 130 0 120 ns interlock time with limitation t li 0 150 0 150 0 150 0 100 0 100 ns minimum interlock time t mli 20 - 20 - 20 - 20 - 20 - ns interlock time without limitation t ui 0-0-0-0-0- ns output release time t az - 10 - 10 - 10 - 10 - 10 ns output delay time t zah 20 - 20 - 20 - 20 - 20 - ns output stabilization time (from release) t zad 0-0-0-0-0- ns envelope time t env 20 70 20 70 20 70 20 55 20 55 ns strobe dmardy delay time t sr -50-30-20-na-nans last strobe time t rfs - 75 - 60 - 50 - 60 - 60 ns pause time t rp 160 - 125 - 100 - 100 - 100 - ns iordy pull-up time t ioryz - 20 - 20 - 20 - 20 - 20 ns iordy wait time t ziory 0-0-0-0-0- ns dmack setup/hold time t ack 20 - 20 - 20 - 20 - 20 - ns strobe stop time t ss 50 - 50 - 50 - 50 - 50 - ns
data sheet s16302ej3v0ds 28 pd720130 serial rom interface block parameter symbol conditions min. max. unit clock frequency t scl 100 khz clock pulse width low t low 4.7 s clock pulse width high t high 4.0 s clock low to data valid t aa 100 4500 ns start hold time t hd.sta 4.0 s start setup time t su.sta 4.7 s data in hold time t hd.dat 0ns data in setup time t su.dat 0.2 s data out hold time t dh 50 ns stop setup time t su.sto 4.7 s time the bus must be free before a new transmission can start t buf 10 s write cycle time t wr 10 ms
data sheet s16302ej3v0ds 29 pd720130 figure 3-6. transmit waveform for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 4 point 3 point 1 point 2 point 5 point 6 figure 3 - 7. transmitter measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
data sheet s16302ej3v0ds 30 pd720130 timing diagram system reset timing resetb t rst remark after reset is negated, this chip read the serial rom first. do not reset while the serial rom is read. the serial rom is completed to read below time, after reset is negated. 5 + 0.1197 bytes (serial rom size) + 0.5678 (ms) example in the case of 512 bytes: 66.855 ms, in the case of 8 kbytes: 986.15 ms usb power-on and connection events t sigatt d + or d ? hub port power ok attatch detected reset recovery time usb system software reads device speed 4.01 v v bus v ih(min) v ih hub port power-on 10 ms t attdb usb differential data jitter for full-speed t period differential data lines crossover points consecutive transitions n t period + t dj1 paired transitions n t period + t dj2
data sheet s16302ej3v0ds 31 pd720130 usb differential-to-eop transition skew and eop width for full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt receiver eop width: t feopr diff. data-to- se0 skew n t period + t fdeop usb receiver jitter tolerance for full-speed differential data lines t period t jr t jr1 t jr2 consecutive transitions n t period + t jr1 paired transitions n t period + t jr2 usb connection sequence on full-speed system bus t hds t sca t cko t scs t fca t drs chirp k device out reversion to full-speed mode fsj fsj pull-up is active. t 0 usb bus usb connection sequence on high-speed system bus t hds t sca t cko t scs t fca chirp k device out reset complete fsj pull-up is active. t 0 usb bus t ssc t csi t rha t fsc chirp state from host/hub reversion to high-speed mode kkjjkj k j
data sheet s16302ej3v0ds 32 pd720130 usb reset sequence from suspend state on full-speed system bus t sca t cko t scs t fca t drs chirp k device out fsj fsj pull-up is active. t 0 usb bus usb reset sequence from suspend state on high-speed system bus t sca t cko t scs t fca chirp k device out reversion to high-speed mode fsj pull-up is active. t 0 usb bus t ssc t csi t rha t fsc chrip state from host/hub reset complete kkjkkj j j usb suspend and resume on full-speed system bus usb bus fsj fsj fsk fs eop t sus power will be down note time required to relock pll and stabilize oscillator. t spd usb suspend and resume on high-speed system bus usb bus fsj fsk high-speed packet t spd t t sus power will be down note time required to relock pll and stabilize oscillator. t csr reversion to full-speed mode t rhs high-speed packet reversion to high-speed mode t 0
data sheet s16302ej3v0ds 33 pd720130 ide pio mode timing t 1 idecs1b, idecs0b ideea2-ideea0 ideiorb ideiowb ided15-ided0 ided15-ided0 ideiordy h l h l h l h l h l t 0 t 2 t 4 t 2i t 5 t 6 t 6z t 3 t a t 9 t c t rd t b (write) (read) ide multi word dma mode timing t 0 h l h l h l h l h l idedrq idedakb ideiorb ideiowb ided15-ided0 (read) ided15-ided0 (write) h l t kr /t kw t m t z t d t e t f t gr t h t i t j t gw t lr /t lw t n idecs1b, idecs0b ide ultra dma mode data-in timing t ack crc t 2cyc t cyc t dvs t dvh t fs t cyc t az t ziory t ack t ioryz t ss t li t mli t ui t zad t zah t env t li t li t az t dvh t dvs t zad t fs t env t ack t ack t ack t ack t ack t ack h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l ideiowb (stop) ideiordy (hdmardy) ideiorb (dstrobe) idea2-idea0 h l idecs1b, idecs0b data data data
data sheet s16302ej3v0ds 34 pd720130 ide ultra dma mode data-in stop timing t sr t rp t rfs h l h l h l h l h l h l idedrq idedakb ided15-ided0 ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) ide ultra dma mode data-in end timing crc t rps t ioryz t rp t li t mli t zah t dvh t dvs t ack t az t ack t li t mli t ack h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) idecs1b, idecs0b idea2-idea0 ide ultra dma mode data-out timing t rfs t rp t ack t ui t ack t ack t ack t ack t ack t li t env t ui t li t mli t ack t ack t ziory t dvs t dvh t 2cyc t cyc t cyc t dvs t dvh t ioryz t mli t li h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l ideiowb (stop) ideiordy (ddmardy) ideiorb (hstrobe) idea2-idea0 h l idecs1b, idecs0b data data data crc
data sheet s16302ej3v0ds 35 pd720130 ide ultra dma mode data-out stop timing t sr t rp t rfs h l h l h l h l h l h l idedrq idedakb ided15-ided0 ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) ide ultra dma mode data-out end timing h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l crc t ioryz t ss t li t mli t dvh t dvs t ack ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) idecs1b, idecs0b idea2-idea0 t li t ack t ack t li ide ultra dma mode data skew timing xstrobe dd0 : : dd15 t 2cyc t cyc t dvs t dvh data data data t ds t dh ideiorb (output side) ided15-ided0 (output side) output side input side delay, skew, etc., by cable ideiordy (input side) ided15-ided0 (input side) h l h l h l h l t cyc
data sheet s16302ej3v0ds 36 pd720130 serial rom access timing scl sda (output) sda (input) t su.sta t hd.sta t su.dat t high t low t low t hd.dat t aa t dh t su.sto t buf serial rom write cycle timing pio1 pio0 word n 8th bit ack stop condition start condition t wr
data sheet s16302ej3v0ds 37 pd720130 4. package drawing ? pd720130gc-9eu 75 76 50 100 1 26 25 51 s 100-pin plastic tqfp (fine pitch) (14x14) item millimeters b 14.0 0.2 d 16.0 0.2 f 1.0 g 1.0 a 16.0 0.2 c 14.0 0.2 h 0.22 0.05 i 0.08 j k note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 1.0 0.2 0.5 (t.p.) a r detail of lead end s m hi g f b c d l 0.5 n 0.08 p 1.0 q 0.1 0.05 p100gc-50-9e u m 0.17 + 0.03 ? 0.07 s 1.1 0.1 t 0.25 u 0.6 0.15 r3 + 4 ? 3 k j p q l u t m s n
data sheet s16302ej3v0ds 38 pd720130 ? pd720130gc-9eu-sin 100-pin plastic tqfp (fine pitch) (14x14) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.0 0.2 14.0 0.2 0.5 (t.p.) 1.0 j 16.0 0.2 k c 14.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 1.0 n p q 0.10 1.0 0.1 0.1 0.05 s100gc-50-9eu- 2 s 1.27 max. h 0.22 + 0.05 ? 0.04 m 0.145 + 0.055 ? 0.045 r3 + 7 ? 3 75 76 50 100 1 26 25 51 s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet s16302ej3v0ds 39 pd720130 5. recommended soldering conditions the pd720130 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact your nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) pd720130gc-9eu: 100-pin plastic tqfp (fine pitch) (14 14) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 partial heating pin temperature: 300 c max., time: 3 seconds or less (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. pd720130gc-9eu-sin: 100-pin plastic tqfp (fine pitch) (14 14) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 partial heating pin temperature: 300 c max., time: 3 seconds or less (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet s16302ej3v0ds 40 pd720130 [memo]
data sheet s16302ej3v0ds 41 pd720130 [memo]
data sheet s16302ej3v0ds 42 pd720130 [memo]
data sheet s16302ej3v0ds 43 pd720130 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd720130 eeprom is a trademark of nec electronics corporation. usb logo is a trademark of usb implementers forum, inc. the information in this document is current as of june, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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